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d a t a sh eet preliminary speci?cation supersedes data of 1999 oct 12 file under integrated circuits, ic01 2000 jan 20 integrated circuits UDA1324TS ultra low-voltage stereo filter dac
2000 jan 20 2 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS features general low power consumption ultra low power supply voltage from 1.9 to 2.7 v selectable control via l3 microcontroller interface or via static pin control system clock frequencies of 256f s , 384f s and 512f s selectable via l3 interface or 256f s and 384f s via static pin control supports sampling frequencies (f s ) from 16 to 48 khz integrated digital filter plus non inverting digital-to-analog converter (dac) no analog post filtering required for dac slave mode only applications easy application small package size (ssop16). multiple format input interface l3 mode: i 2 s-bus, msb-justified or lsb-justified 16, 18 and 20 bits format compatible static pin mode: i 2 s-bus or lsb-justified 16, 18 and 20 bits format compatible 1f s input format data rate. dac digital sound processing digital logarithmic volume control in l3 mode digital de-emphasis selection for 32, 44.1 and 48 khz sampling frequencies in l3 mode or 44.1 khz sampling frequency in static pin mode soft mute control in static pin mode or in l3 mode. advanced audio con?guration stereo line output (volume control in l3 mode) high linearity, wide dynamic range and low distortion. applications portable digital audio equipment. general description the UDA1324TS is a single-chip stereo dac employing bitstream conversion techniques. the ultra low-voltage requirements make the device eminently suitable for use in portable digital audio equipment which incorporates playback functions. the UDA1324TS supports the i 2 s-bus data format with word lengths of up to 20 bits, the msb-justified data format with word lengths of up to 20 bits and the lsb-justified serial data format with word lengths of 16, 18 and 20 bits. the UDA1324TS can be used in two modes: l3 mode or static pin mode. in the l3 mode, all digital sound processing features must be controlled via the l3 interface, including the selection of the system clock setting. in the two static modes, the UDA1324TS can be operated in the 256f s and 384f s system clock mode. muting, de-emphasis for 44.1 khz and four digital input formats (i 2 s-bus or lsb-justified 16, 18 and 20 bits) can be selected via static pins. the l3 interface cannot be used in this application mode, so volume control is not available in this mode. ordering information type number package name description version UDA1324TS ssop16 plastic shrink small outline package; 16 leads; body width 4.4 mm sot369-1
2000 jan 20 3 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS quick reference data notes 1. the analog performance figures are measured at 2.0 v supply voltage. 2. the dac output voltage scales linearly with the power supply voltage. block diagram symbol parameter conditions min. typ. max. unit supplies v dda analog supply voltage 1.9 2.0 2.7 v v ddd digital supply voltage 1.9 2.0 2.7 v i dda analog supply current v dda = 2.0 v - 3.0 - ma i ddd digital supply current v ddd = 2.0 v - 1.5 - ma dac; note 1 v o(rms) output voltage (rms value) note 2 - 500 - mv (thd + n)/s total harmonic distortion-plus-noise to signal ratio at 0 db -- 83 - 78 db at - 60 db; a-weighted -- 36 - db s/n signal-to-noise ratio code = 0; a-weighted - 97 - db a cs channel separation - 100 - db t amb ambient temperature - 40 - +70 c fig.1 block diagram. handbook, full pagewidth mbk770 dac UDA1324TS noise shaper interpolation filter volume/mute/de-emphasis control interface 14 15 dac 6 digital interface 8 16 9 10 3 2 1 4 5 11 7 13 12 voutr bck v ssa ws voutl datai v dda v ddd v ref(dac) v ssd appl0 sysclk appl1 appsel appl2 appl3
2000 jan 20 4 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS pinning functional description system clock the UDA1324TS operates in the slave mode only. therefore, in all applications the system devices must provide the system clock. the system frequency (f sys ) is selectable and depends on the application mode. the options are: 256f s , 384f s and 512f s for the l3 mode and 256f s or 384f s for the static pin mode. the system clock must be locked in frequency to the digital interface input signals. the UDA1324TS supports sampling frequencies (f s ) from 16 to 48 khz. application modes the application mode can be set with the three-level pin appsel (see table 1): l3 mode static pin mode with f sys = 384f s static pin mode with f sys = 256f s . table 1 selecting application mode and system clock frequency via pin appsel the function of an application input pin (active high) depends on the application mode (see table 2). table 2 functions of application input pins for example, in the static pin mode the output signal can be soft muted by setting pin appl0 to high. de-emphasis can be switched on for 44.1 khz by setting pin appl1 to high; setting pin appl1 to low will disable de-emphasis. symbol pin description bck 1 bit clock input ws 2 word select input datai 3 data input v ddd 4 digital supply voltage v ssd 5 digital ground sysclk 6 system clock input: 256f s , 384f s and 512f s appsel 7 application mode select input appl3 8 application input pin 3 appl2 9 application input pin 2 appl1 10 application input pin 1 appl0 11 application input pin 0 v ref(dac) 12 dac reference voltage v dda 13 analog supply voltage for dac voutl 14 left channel output v ssa 15 analog ground for dac voutr 16 right channel output fig.2 pin configuration. handbook, halfpage UDA1324TS mbk769 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 voutr bck v ssa ws voutl datai v dda v ddd v ref(dac) v ssd appl0 sysclk appl1 appsel appl2 appl3 voltage on pin appsel mode f sys v ssd l3 mode 256f s , 384f s or 512f s 0.5v ddd static pin mode 384f s v ddd 256f s pin function l3 mode static pin mode appl0 test mute appl1 l3clock deem appl2 l3mode sf0 appl3 l3data sf1
2000 jan 20 5 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS in the l3 mode, pin appl0 must be set to low. it should be noted that when the l3 mode is used, an initialization must be performed when the ic is powered-up. digital interface d ata formats the digital interface of the UDA1324TS supports multiple format inputs (see fig.3). left and right data-channel words are time multiplexed. the ws signal must have a 50% duty factor for all lsb-justified formats. the bck clock can be up to 64f s , or in other words the bck frequency is 64 times the word select (ws) frequency or less: f bck 64 f ws . important : the ws edge must fall on the negative edge of the bck at all times for proper operation of the digital interface. the UDA1324TS also accepts double speed data for double speed data monitoring purposes. l3 mode i 2 s-bus format with data word length of up to 20 bits msb-justified format with data word length up to 20 bits lsb-justified format with data word length of 16, 18 or 20 bits. s tatic pin mode i 2 s-bus format with data word length of up to 20 bits lsb-justified format with data word length of 16, 18 or 20 bits. these four formats are selectable via the static pin codes sf0 and sf1 (see table 3). table 3 input format selection using sf0 and sf1 interpolation ?lter the digital filter interpolates from 1f s to 128f s by cascading a recursive filter and a fir filter (see table 4). table 4 interpolation ?lter characteristics noise shaper the 3rd-order noise shaper operates at 128f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter (fsdac). filter stream dac the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post filter is not needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage capable of driving a line output. the output voltage of the fsdac scales linearly with the power supply voltage. format sf0 sf1 i 2 s-bus 0 0 lsb-justi?ed 16 bits 0 1 lsb-justi?ed 18 bits 1 0 lsb-justi?ed 20 bits 1 1 item condition value (db) pass-band ripple 0 to 0.45f s 0.1 stop band >0.55f s - 50 dynamic range 0 to 0.45f s 108
2000 jan 20 6 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... n dbook, full pagewidth 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb msb msb b2 2 1 > = 8 12 3 left i 2 s-bus format ws bck data right 3 > = 8 msb b2 mbl121 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb 16 msb b2 b3 b4 left lsb-justified format 18 bits ws bck data right 15 18 17 2 1 msb b2 b3 b4 b17 lsb 16 15 18 17 2 1 b17 lsb msb-justified format ws left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 b2 > = 8 > = 8 bck data fig.3 digital interface input data formats.
2000 jan 20 7 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS l3 interface the following system and digital sound processing features can be controlled in the l3 mode of the UDA1324TS: system clock frequency data input format de-emphasis for 32, 44.1 and 48 khz volume soft mute. the exchange of data and control information between the microcontroller and the UDA1324TS is accomplished through a serial interface comprising the following signals: l3data l3mode l3clock. information transfer through the microcontroller bus is organized in accordance with the l3 interface format, in which two different modes of operation can be distinguished: address mode and data transfer mode. address mode the address mode (see fig.4) is required to select a device communicating via the l3 interface and to define the destination registers for the data transfer mode. data bits 7 to 2 represent a 6-bit device address where bit 7 is the msb. the address of the UDA1324TS is 000101 (bit 7 to bit 2). if the UDA1324TS receives a different address, it will deselect its microcontroller interface logic. data transfer mode the selected address remains active during subsequent data transfers until the UDA1324TS receives a new address command. the fundamental timing of data transfers (see fig.5) is essentially the same as the address mode. the maximum input clock frequency and data rate is 64f s . data transfer can only be in one direction, consisting of input to the UDA1324TS to program sound processing and other functional features. all data transfers are by 8-bit bytes. data will be stored in the UDA1324TS after reception of a complete byte. a multi-byte transfer is illustrated in fig.6. registers the sound processing and other feature values are stored in independent registers. the first selection of the registers is achieved by the choice of data type that is transferred. this is performed in the address mode using bit 1 and bit 0 (see table 5). table 5 selection of data transfer the second selection is performed by the 2 msbs of the data byte (bit 7 and bit 6). the other bits in the data byte (bit 5 to bit 0) represent the value that is placed in the selected registers. the status settings are given in table 6 and the data settings are given in table 7. bit 1 bit 0 transfer 0 0 data (volume, de-emphasis, mute) 0 1 not used 1 0 status (system clock frequency, data input format) 1 1 not used
2000 jan 20 8 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS handbook, full pagewidth t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgl723 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a fig.4 timing address mode. handbook, full pagewidth t stp(l3) t stp(l3) t su(l3)d t su(l3)da t h(l3)da t h(l3)d mgl882 t cy(clk)l3 l3mode l3clock t clk(l3)h t clk(l3)l bit 0 l3data write bit 7 fig.5 timing data transfer mode.
2000 jan 20 9 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS handbook, full pagewidth t stp(l3) address l3data l3clock l3mode address data byte #1 data byte #2 mgl725 fig.6 multibyte data transfer. programming the features when the data transfer of type status is selected, the features for the system clock frequency and the data input format can be controlled. table 6 data transfer of type status when the data transfer of type data is selected, the features for volume, de-emphasis and mute can be controlled. table 7 data transfer of type data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register selected 0 0 sc1 sc0 if2 if1 if0 0 sc = system clock frequency (2 bits); see table 8 if = data input format (3 bits); see table 9 10000000 not used bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register selected 0 0 vc5 vc4 vc3 vc2 vc1 vc0 vc = volume control (6 bits); see table 11 01000000 not used 1 0 0 de1 de0 mt 0 0 de = de-emphasis (2 bits); see table 10 mt = mute (1 bit); see table 12 11000001def ault setting
2000 jan 20 10 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS s ystem clock frequency the system clock frequency is a 2-bit value to select the external clock frequency. table 8 system clock settings d ata format the data format is a 3-bit value to select the used data format. table 9 data input format settings d e - emphasis de-emphasis is a 2-bit value to enable the digital de-emphasis filter. table 10 de-emphasis settings v olume control the volume control is a 6-bit value to program the volume attenuation from 0 to - 60 db and - db in steps of 1 db. table 11 volume settings m ute mute is a 1-bit value to enable the digital mute. table 12 mute setting sc1 sc0 function 0 0 512f s 0 1 384f s 1 0 256f s 1 1 not used if2 if1 if0 format 000i 2 s-bus 0 0 1 lsb-justi?ed 16 bits 0 1 0 lsb-justi?ed 18 bits 0 1 1 lsb-justi?ed 20 bits 1 0 0 msb-justi?ed 1 0 1 not used 1 1 0 not used 1 1 1 not used de1 de0 function 0 0 no de-emphasis 0 1 de-emphasis, 32 khz 1 0 de-emphasis, 44.1 khz 1 1 de-emphasis, 48 khz vc5 vc4 vc3 vc2 vc1 vc0 volume (db) 000000 0 000001 0 000010 - 1 000011 - 2 :::::: : 110011 - 51 110100 110101 - 52 110110 110111 - 54 111000 111001 - 57 111010 111011 111100 - 60 111101 111110 - 111111 mt function 0 no muting 1 muting
2000 jan 20 11 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. all supply connections must be made to the same power supply. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor, except pin 14 which can withstand esd pulses of - 2500 to +2500 v. 3. equivalent to discharging a 200 pf capacitor via a 2.5 m h series inductor. 4. short-circuit test at t amb =0 c and v dda = 3 v. dac operation after short-circuiting cannot be warranted. handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. thermal characteristics quality specification in accordance with snw-fq-611-e . dc characteristics v ddd =v dda = 2.0 v; t amb =25 c; r l =5k w ; all voltages referenced to ground (pins v ssa and v ssd ); unless otherwise speci?ed. symbol parameter conditions min. max. unit v ddd digital supply voltage note 1 - 5.0 v v dda analog supply voltage note 1 - 5.0 v t xtal(max) maximum crystal temperature - 150 c t stg storage temperature - 65 +125 c t amb ambient temperature - 40 +85 c v es electrostatic handling voltage note 2 - 3000 +3000 v note 3 - 300 +300 v i sc(dac) short-circuit current of dac note 4 output short-circuited to v ssa(dac) - 450 ma output short-circuited to v dda(dac) - 300 ma symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 190 k/w symbol parameter conditions min. typ. max. unit supplies v dda analog supply voltage note 1 1.9 2.0 2.7 v v ddd digital supply voltage note 1 1.9 2.0 2.7 v i dda analog supply current operating - 3.0 - ma i ddd digital supply current operating - 1.5 - ma
2000 jan 20 12 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS notes 1. all supply connections must be made to the same external power supply unit. 2. when the dac drives a capacitive load above 50 pf, a series resistance of 100 w must be used to prevent oscillations in the output operational amplifier. ac characteristics v ddd =v dda = 2.0 v; f i = 1 khz; t amb =25 c; r l =5k w ; all voltages referenced to ground (pins v ssa and v ssd ); unless otherwise speci?ed. digital inputs: pins bck, ws, datai, sysclk, appl0, appl1, appl2 and appl3 v ih high-level input voltage 0.8v ddd -- v v il low-level input voltage -- 0.2v ddd v ? i li ? input leakage current -- 1 m a c i input capacitance -- 10 pf three-level input: pin appsel v ih high-level input voltage 0.8v ddd - v ddd + 0.5 v v im middle-level input voltage 0.3v ddd - 0.7v ddd v v il low-level input voltage - 0.5 - 0.2v ddd v dac v ref(dac) reference voltage referenced to v ssa 0.45v dda 0.5v dda 0.55v dda v i o(max) maximum output current (thd + n)/s < 0.1%; r l =5k w - 0.16 - ma r o output resistance - 0.15 2.0 w r l load resistance 3 -- k w c l load capacitance note 2 -- 50 pf symbol parameter conditions min. typ. max. unit dac v o(rms) output voltage (rms value) - 500 - mv d v o unbalance voltage between channels - 0.1 - db (thd + n)/s total harmonic distortion-plus-noise to signal ratio at 0 db -- 83 - 78 db at - 60 db; a-weighted -- 36 - db s/n signal-to-noise ratio code = 0; a-weighted - 97 - db a cs channel separation - 100 - db psrr power supply ripple rejection ratio f ripple = 1 khz; v ripple = 100 mv (p-p) - 50 - db symbol parameter conditions min. typ. max. unit
2000 jan 20 13 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS timing v ddd =v dda = 1.9 to 2.7 v; t amb = - 40 to +85 c; r l =5k w ; all voltages referenced to ground (pins v ssa and v ssd ); unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit system clock (see fig.7) t sys system clock cycle time f sys = 256f s 78 88 244 ns f sys = 384f s 52 59 162 ns f sys = 512f s 39 44 122 ns t cwl low-level system clock pulse width f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns t cwh high-level system clock pulse width f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns digital interface with i 2 s-bus (see fig.8) t cy(bck) bit clock cycle time 300 -- ns t bckh bit clock high time 100 -- ns t bckl bit clock low time 100 -- ns t r rise time -- 20 ns t f fall time -- 20 ns t su(datai) data input set-up time 20 -- ns t h(datai) data input hold time 0 -- ns t su(ws) word select set-up time 20 -- ns t h(ws) word select hold time 10 -- ns control l3 interface (see figs 4 and 5) t cy(clk)l3 l3clock cycle time 500 -- ns t clk(l3)h l3clock high time 250 -- ns t clk(l3)l l3clock low time 250 -- ns t su(l3)a l3mode set-up time for address mode 190 -- ns t h(l3)a l3mode hold time for address mode 190 -- ns t su(l3)d l3mode set-up time for data transfer mode 190 -- ns t h(l3)d l3mode hold time for data transfer mode 190 -- ns t su(l3)da l3data set-up time for data transfer and address mode 190 -- ns t h(l3)da l3data hold time for data transfer and address mode 30 -- ns t stp(l3) l3mode stop time for data transfer mode 190 -- ns
2000 jan 20 14 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS handbook, full pagewidth mgr984 t sys t cwh t cwl fig.7 system clock timing. handbook, full pagewidth mgl880 t f t h(ws) t su(ws) t su(datai) t h(datai) t bckh t bckl t cy(bck) t r ws bck datai fig.8 i 2 s-bus timing.
2000 jan 20 15 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS application information fig.9 application diagram. handbook, full pagewidth mbk771 47 w r1 UDA1324TS 6 sysclk system clock 1 bck 2 ws 3 datai 14 voutl r4 100 w r5 10 k w 16 voutr r6 100 w r7 10 k w 7 appsel 10 appl1 9 appl2 8 appl3 11 appl0 47 m f (16 v) c3 47 m f (16 v) c2 left output right output 12 v ref(dac) c4 47 m f (16 v) c7 100 nf (63 v) 4 5 v ddd v ssd r3 1 w digital supply voltage c6 15 13 v ssa v dda r2 1 w c1 100 m f (16 v) c5 100 nf (63 v) 100 nf (63 v) analog supply voltage
2000 jan 20 16 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.00 1.4 1.2 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 0.65 0.45 0.48 0.18 10 0 o o 0.13 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 0.75 0.45 1.0 sot369-1 mo-152 95-02-04 99-12-27 w m q a a 1 a 2 b p d y h e l p q detail x e z e c l v m a x (a ) 3 a 0.25 18 16 9 pin 1 index 0 2.5 5 mm scale ssop16: plastic shrink small outline package; 16 leads; body width 4.4 mm sot369-1 a max. 1.5
2000 jan 20 17 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 jan 20 18 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
2000 jan 20 19 philips semiconductors preliminary speci?cation ultra low-voltage stereo ?lter dac UDA1324TS notes
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